1. Field of the Invention
The present invention relates to an electronic device with a serial AT Attachment (ATA) interface, and more particularly to an electronic device of this type, represented by a disk drive, suitable for power saving, and a power-saving control method for use in the electronic device.
2. Description of the Related Art
Standards for serial ATA (SATA) interfaces have recently been established. Serial ATA interfaces are used as interfaces between a peripheral device represented by a hard disk drive and a host (host system) represented by a personal computer. In this point, serial ATA interfaces are similar to conventional ATA interfaces (i.e., parallel ATA interfaces).
A peripheral device having the serial ATA interface, such as a hard disk drive (HDD), is connected to a host by a serial ATA bus. In such an HDD, to secure compatibility with a parallel ATA interface, it is necessary to convert a parallel ATA interface into a serial ATA interface, and convert a serial ATA interface into a parallel ATA interface. Such interface conversion is performed by, for example, an LSI (bridge LSI) called a serial ATA interface control circuit (serial ATA bridge). A serial ATA interface control circuit is provided for the HDD.
The standards for serial ATA interfaces (hereinafter referred to as “the serial ATA standards”) stipulate three layers of different functions, i.e., a physical layer, link layer and transport layer. The physical layer interprets received data, and transmits the data to the link layer in accordance with the interpretation result. The physical layer has a function for executing high-rate serial data transmission and reception. The physical layer also outputs a serial data signal to the link layer in response to a request therefrom. The link layer supplies the physical layer with a request to output a signal. The physical layer also supplies the transport layer with the data transmitted from the physical layer. The transport layer performs conversion for an operation conforming to the standards for parallel ATA interfaces (hereinafter referred to as “the parallel ATA standards”). Assuming that the above-mentioned serial ATA interface control circuit is used in an HDD, the role of the transport layer corresponds to the role of the ATA signal output unit of a conventional host that utilizes a parallel ATA connection.
The serial ATA interface control circuit has processing units for performing process related to the physical layer, link layer and transport layer. The serial ATA interface control circuit is connected to the disk controller (HDC) of the HDD via a parallel ATA bus (or a bus compliant with the parallel ATA bus) based on the ATA interface standards. Accordingly, in the connection between the serial ATA interface control circuit and HDC of the HDD, operations equivalent to those stipulated in the ATA interface standards or conforming to the standards are performed.
The serial ATA standards stipulate three power management modes for serial ATA interfaces, i.e., “PHY READY (Idle)”, “Partial” and “Slumber” modes. The “Idle (PHY READY)” mode indicates a mode (non power-saving mode) for setting a non power-saving state. The non power-saving state means a state in which a physical-layer processing unit for realizing the operation of the physical layer and a main phase-locked loop (PLL) circuit operate, and the interface states of a host and peripheral device are synchronized with each other. The “Partial” mode and “Slumber” mode are modes (power-saving modes) for setting a power-saving state. The power-saving state means that the physical-layer processing unit is operating, and an interface signal is in a neutral logic state.
The difference by definition between the “Partial” mode and “Slumber” mode lies in the time required for restoration therefrom to the “PHY READY (Idle)” mode. More specifically, it is stipulated that the time required for restoration from the “Partial” mode must not exceed 10 μs. On the other hand, it is stipulated that the time required for restoration from the “Slumber” mode must not exceed 10 ms. As long as the restoration time and interface power state conform to the standards, manufacturers can select the portion of a device, the power-saving function of which should be executed in the “Partial” or “Slumber” mode (i.e., can select the circuit that should be turned off in the mode).
The serial ATA standards stipulate the procedure of transition from the “PHY READY (Idle)” mode (i.e., non power-saving mode) to the “Partial” or “Slumber” mode (i.e., power-saving mode), and the procedure of restoration from the “Partial” or “Slumber” mode. However, they do not stipulate the minimum time ranging from the time when the state is once shifted, to the time when a restoration operation is performed.
Jpn. Pat. Appln. KOKAI Publication No. 2000-181584 discloses a technique (hereinafter referred to as “the prior art”) for saving the power of an apparatus having a serial interface circuit. This prior art is employed in a serial interface circuit for periodically performing a communication operation, such as one based on the IEEE 1394 serial interface. The prior art is characterized in that the stopping of the periodic supply of a clock to a serial interface circuit and restart of the periodic supply are controlled. In other words, in the prior art, the power saving of the apparatus is realized by controlling periodic stop and restart of the operation of the serial interface circuit. However, power saving is realized only when the serial interface circuit periodically performs a communication operation.
In contrast, the power-saving mode stipulated in the serial ATA standards is controllable from both the host side and peripheral device side. Therefore, immediately after the host or peripheral device sets an arbitrary power-saving mode, the node of the host or peripheral device may determine that restoration from a power-saving state to an “Idle” state (non power-saving state) is needed. In general, a node that tries to be restored from the power-saving state to the “Idle” state can confirm its power-saving state. However, this node cannot confirm the power-saving state (in particular, the transitional state) of another node (hereinafter referred to as “the connected node”) connected to the first-mentioned node. Accordingly, the node that tries to be restored from the power-saving state to the “Idle” state issues a restoration request to the connected node, regardless of the power-saving state of the connected node.
A consideration will now be given to the power-saving operation of an electronic circuit formed of a plurality of circuit elements. In this case, each circuit element as a preset target of power saving generally has a power-saving structure unique thereto. In a circuit of this type, to complete the operation of transition to a power-saving state, it is necessary to shift all preset circuit elements to a designated power-saving state. The shift of each circuit element to a power-saving state is performed by a predetermined procedure. Accordingly, in the above-mentioned electronic circuit, an intermediate state in which transition to a power-saving state is occurring exists until all circuit elements as power-saving targets are shifted to the designated power-saving state.
Assume here that a node has supplied a request for restoration from a power-saving state, to another node connected thereto and incorporating a plurality of electronic circuits that are now in the above-mentioned intermediate state. In this case, it is possible that the restoration request fails to reach the electronic circuits in the node. If the restoration request fails to be received, restoration from the power-saving state cannot reliably be performed. Such a restoration error occurs when, for example, some circuit elements are still operating and others have shifted to the power-saving state. Furthermore, the circuit elements may require a predetermined period to shift to the power-saving state. In other words, the circuit elements may assume the above-mentioned intermediate state. Also in this case, a restoration error similar to the above may well occur.